Listing 2 and Listing 3 in the accompanying document, named
‘KD6028_6002_Workshop_2021_22.pdf’, show the algorithmic description of the multiplier
‘BoothModMultAlg’ and associated test–bench. Create a new Xilinx ISE project (targeting the
correct CPLD device etc.) and copy the source text from listings 2 and 3 into two separate
simulation source files – ‘BoothModMultAlg.v’ and ‘test_BoothModMultAlg.v’. Perform a
behavioural simulation of the test–module and capture the results in waveform format, providing a
full view and zoomed–in view, in order to confirm correct operation. Try changing the value of the

5 local parameter ‘N’ in the test–module (even number) to verify that the algorithm works for a variety
of input word lengths. Briefly comment on all results