Accumulator and BMM_FSM_NC.
Figures 4, 5, 7 and 8, in the associated document ‘KD6028_6002_Workshop_2021_22.pdf’, show
the internal logic structure of each of the four sub–modules comprising the signed 8–bit x 8–bit
multiplier, ‘BoothModMult’, module.
Create Verilog–HDL source behavioural–style descriptions for each of the four sub–modules
contained within the design, based on the provided logic structures. Provide syntax–error–free
listings of the sources in your report. It may be useful to perform quick standalone interactive
simulation of each module prior to using them in the top–level module, however it is not required to
include the results of these in your report.