The system shown in figure 2 makes use of a 16–bit test pattern generator (PattGen – PG1) to
produce the input values for the signed multiplier. The patter generator can be configured to
produce pseudo–random test patterns or fixed test patterns, depending on the logic level applied to
the ‘FixRand’ input. A separate Logisim Evolution circuit is provided on eLearning named
‘PseudoRandom16.circ’, having the same internal logic as the random pattern generator part of
the ‘PattGen’ module. Figure 3 shows the Logisim circuit.